FIGS. 1A to 1N show structures of related components in steps of a method of prior art for fabricating a shield gate trench MOSFET, wherein a bottom up methodology is adopted to form a trench detached gate structure with a shield gate, via the following steps:
Step one: as is shown on FIG. 1A, providing a semiconductor substrate 101, such as a silicon substrate; forming a hard mask layer 102 on a surface of the semiconductor substrate 101, the hard mask layer adopting an oxidative layer or an oxidative layer plus a nitride layer.
Subsequently, as is shown on FIG. 1B, etching the hard mask layer 102 by means of lithography to define a gate forming region, and etching the semiconductor substrate 101 with the hard mask layer as a mask to form a trench 103.
Step two: forming an oxidative layer 104 on a side and a bottom of the trench 103, as is shown on FIG. 1C.
Step three: filling in an source polysilicon 105 in the trench 103, as is shown on FIG. 1D, the source polysilicon 105 being a shield polysilicon and being generally connected with a source to form a shield gate.
Step four: etching back the source polysilicon 105, as is shown on FIG. 1E, to remove the source polysilicon 105 outside of the trench 103, with a top of the source polysilicon 105 inside of the trench 103 being level with the semiconductor substrate 101.
Removing the oxidative layer 104 on a top of the trench 103, as is shown on FIG. 1F.
Step five: conducting thermal oxidation and forming at the same time a gate oxide 106a and a inter-poly dielectric isolation layer 106b, as is shown on FIG. 1G.
Forming a polysilicon gate 107, which being a trench gate, as is shown on FIG. 1H.
Etching back the polysilicon gate 107 rendering the polysilicon gate 107 only remain on two sides of the source polysilicon 105 on the top of the trench 103, as is shown on FIG. 1I; it can be instantly seen that the polysilicon gate 107 on the two sides of the trench 103 are detached and such a detached trench gate forming on the side walls of a trench is referred to as a trench detached side gate, as is opposed to a trench gate composed of a polysilicon gate completely filled in on the top of the trench.
Step six: forming a well region 108 and a source region 109, as is shown on Figure H.
Forming an interlayer film 110 and a contact hole 111a corresponding to a structure previous to filling of metals, as is shown on FIG. 1J. Preferably, subsequent to the etching and forming of the contact hole 111a, a well region contact region needs to be formed at a bottom of the contact hole 111a corresponding to a top of the source region 109.
Subsequently filling the metals in the contact hole 111a to transform the contact hole 111a to a contact hole 111, as is shown on FIG. 1K.
Forming a positive metal layer 112, as is shown on FIG. 1L.
Patternizing the positive metal layer 112 by means of lithographic etching to form a source pole and a gate pole, as is shown on FIG. 1M, wherein the source pole is in contact with the source region 109 at the bottom, the well region contact region, and the source polysilicon 105 via the contact hole, and the gate pole is in contact with the polysilicon gate 107 via the contact hole.
Subsequently forming a drain region and a reverse metal layer 113 on a reverse side of the semiconductor substrate 101, and a drain pole comprised of the reverse metal layer 113, as is shown on FIG. 1N.
In the prior art process, a side of the polysilicon gate 107 is detached from the well region 108 via the gate oxide 106a, while a surface of the well region covered by the side of the polysilicon gate 107 is employed to form a channel. As is exemplified by FIG. 1N, the polysilicon gate 107 formed by the aforementioned process only appears on the side walls on the top of the trench, and such a vertical device with a side wall polysilicon structure increases operation current; at the same time, the source polysilicon 105, which being filled in the entire trench, and having good shield effect and relatively small bottom capacitance, reduces input capacitance from source drain and gate drain and improves frequency characteristics.
As can be inferred from the above, the aforementioned polysilicon gate with a side wall polysilicon structure is a trench gate MOSFET with a detached side gate structure having a shield gate, and is also named as a shield gate trench MOSFET with both a left and right structure, and is fabricated in prior art with a bottom up technique. As is shown on FIG. 1G, the gate oxide 106a and a spacer layer of the shield gate, i.e., the inter-poly dielectric isolation layer 106b are formed at the same time, and hence a spacing level between the trench gate, i.e., the polysilicon gate 107 and the shield gate, i.e., the source polysilicon 105 is determined by the gate oxide 106a, restricting application of the structure in low threshold electric appliances, as a thin gate oxide 106a easily results in gate-source current leakage. In conclusion, a low threshold electric appliance requires a thin gate oxide 106a, while a thin gate oxide 106a reduces thickness of the inter-poly dielectric isolation layer 106b, resulting in gate-source current leakage, that is to say, the prior art technique is unable to resolve the conflict between a reduced threshold voltage and a reduced gate-source current leakage.